View SST36VF1601C-70-4C-B3KE_735803.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

16 Mbit (x8/x16) Dual-Bank Flash Memory
SST36VF1601C / SST36VF1602C
SST36VF1601C / 1602C16Mb (x8/x16) Dual-Bank Flash Memory
Data Sheet
FEATURES:
* Organized as 1M x16 or 2M x8 * Dual Bank Architecture - 16 Mbit Bottom Sector Protection - SST36VF1601C: 12 Mbit + 4 Mbit - 16 Mbit Top Sector Protection - SST36VF1602C: 4 Mbit + 12 Mbit * Single 2.7-3.6V for Read and Write Operations * Superior Reliability - Endurance: 100,000 cycles (typical) - Greater than 100 years Data Retention * Low Power Consumption: - Active Current: 6 mA typical - Standby Current: 4 A typical - Auto Low Power Mode: 4 A typical * Hardware Sector Protection/WP# Input Pin - Protects the 4 outermost sectors (8 KWord) in the larger bank by driving WP# low and unprotects by driving WP# high * Hardware Reset Pin (RST#) - Resets the internal state machine to reading array data * Byte# Pin - Selects 8-bit or 16-bit mode * Sector-Erase Capability - Uniform 2 KWord sectors * Chip-Erase Capability * Block-Erase Capability - Uniform 32 KWord blocks * Erase-Suspend / Erase-Resume Capabilities * Security ID Feature - SST: 128 bits - User: 128 bits * Fast Read Access Time - 70 ns * Latched Address and Data * Fast Erase and Program (typical): - Sector-Erase Time: 18 ms - Block-Erase Time: 18 ms - Chip-Erase Time: 35 ms - Program Time: 7 s * Automatic Write Timing - Internal VPP Generation * End-of-Write Detection - Toggle Bit - Data# Polling - Ready/Busy# pin * CMOS I/O Compatibility * Conforms to Common Flash Memory Interface (CFI) * JEDEC Standards - Flash EEPROM Pinouts and command sets * Packages Available - 48-ball TFBGA (6mm x 8mm) - 48-lead TSOP (12mm x 20mm) - Non-Pb (lead-free) packages available * All non-Pb (lead-free) devices are RoHS compliant
PRODUCT DESCRIPTION
The SST36VF1601C and SST36VF1602C are 1M x16 or 2M x8 CMOS Read/Write Flash Memory manufactured with SST's proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The devices write (Program or Erase) with a 2.7-3.6V power supply and conform to JEDEC standard pinouts for x8/x16 memories. Featuring high performance Program, these devices provide a typical Program time of 7 sec and use the Toggle Bit, Data# Polling, or RY/BY# to detect the completion of the Program or Erase operation. To protect against inadvertent write, the devices have on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with a guaranteed endurance of 10,000 cycles. Data retention is rated at greater than 100 years. These devices are suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, the devices significantly improve performance and reliability, while lowering power consumption. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. These devices also improve flexibility while lowering the cost for program, data, and configuration storage applications.
(c)2006 Silicon Storage Technology, Inc. S71249-06-000 1/06 1
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. These specifications are subject to change without notice.
16 Mbit Dual-Bank Flash Memory SST36VF1601C / SST36VF1602C
Data Sheet SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. To meet high-density, surface-mount requirements, these devices are offered in 48-ball TFBGA and 48-lead TSOP packages. See Figures 5 and 6 for pin assignments.
Program Operation
These devices are programmed on a word-by-word or byte-by-byte basis depending on the state of the BYTE# pin. Before programming, one must ensure that the sector which is being programmed is fully erased. The Program operation is accomplished in three steps: 1. Software Data Protection is initiated using the three-byte load sequence. 2. Address and data are loaded. During the Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE# or WE#, whichever occurs first. 3. The internal Program operation is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed typically within 7 s. See Figures 8 and 9 for WE# and CE# controlled Program operation timing diagrams and Figure 23 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands issued during an internal Program operation are ignored.
Device Operation
Memory operation functions are initiated using standard microprocessor write sequences. A command is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first.
Auto Low Power Mode
These devices also have the Auto Lower Power mode which puts them in a near standby mode within 500 ns after data has been accessed with a valid Read operation. This reduces the IDD active Read current to 4 A typically. While CE# is low, the devices exit Auto Low Power mode with any address transition or control signal transition used to initiate another Read cycle, with no access time penalty.
Read Operation
The Read operation is controlled by CE# and OE#; both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in a high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 7).
Sector- (Block-) Erase Operation
These devices offer both Sector-Erase and Block-Erase operations. These operations allow the system to erase the devices on a sector-by-sector (or block-by-block) basis. The sector architecture is based on a uniform sector size of 2 KWord. The Block-Erase mode is based on a uniform block size of 32 KWord. The Sector-Erase operation is initiated by executing a six-byte command sequence with a SectorErase command (30H) and sector address (SA) in the last bus cycle. The Block-Erase operation is initiated by executing a six-byte command sequence with Block-Erase command (50H) and block address (BA) in the last bus cycle. The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or 50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. Any commands issued during the Sector- or Block-Erase operation are ignored except Erase-Suspend and EraseResume. See Figures 13 and 14 for timing waveforms.
(c)2006 Silicon Storage Technology, Inc.
S71249-06-000
1/06
2
16 Mbit Dual-Bank Flash Memory SST36VF1601C / SST36VF1602C
Data Sheet
Chip-Erase Operation
The devices provide a Chip-Erase operation, which allows the user to erase all sectors/blocks to the "1" state. This is useful when a device must be quickly erased. The Chip-Erase operation is initiated by executing a sixbyte command sequence with Chip-Erase command (10H) at address 555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid Read is Toggle Bit or Data# Polling. Any commands issued during the Chip-Erase operation are ignored. See Table 5 for the command sequence, Figure 12 for timing diagram, and Figure 27 for the flowchart. When WP# is low, any attempt to Chip-Erase will be ignored.
The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Ready/Busy# (RY/ BY#), a Data# Polling (DQ7), or Toggle Bit (DQ6) Read may be simultaneous with the completion of the Write cycle. If this occurs, the system may get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both Reads are valid, then the Write cycle has completed, otherwise the rejection is valid.
Ready/Busy# (RY/BY#)
The devices include a Ready/Busy# (RY/BY#) output signal. RY/BY# is an open drain output pin that indicates whether an Erase or Program operation is in progress. Since RY/BY# is an open drain output, it allows several devices to be tied in parallel to VDD via an external pull-up resistor. After the rising edge of the final WE# pulse in the command sequence, the RY/BY# status is valid. When RY/BY# is actively pulled low, it indicates that an Erase or Program operation is in progress. When RY/BY# is high (Ready), the devices may be read or left in standby mode.
Erase-Suspend/Erase-Resume Operations
The Erase-Suspend operation temporarily suspends a Sector- or Block-Erase operation thus allowing data to be read from any memory location, or program data into any sector/block that is not suspended for an Erase operation. The operation is executed by issuing a one-byte command sequence with Erase-Suspend command (B0H). The device automatically enters read mode within 20 s after the Erase-Suspend command had been issued. Valid data can be read from any sector or block that is not suspended from an Erase operation. Reading at address location within erase-suspended sectors/blocks will output DQ2 toggling and DQ6 at "1". While in Erase-Suspend mode, a Program operation is allowed except for the sector or block selected for Erase-Suspend. To resume Sector-Erase or Block-Erase operation which has been suspended, the system must issue an Erase-Resume command. The operation is executed by issuing a one-byte command sequence with Erase Resume command (30H) at any address in the one-byte sequence.
Byte/Word (BYTE#)
The device includes a BYTE# pin to control whether the device data I/O pins operate x8 or x16. If the BYTE# pin is at logic "1" (VIH) the device is in x16 data configuration: all data I/0 pins DQ0-DQ15 are active and controlled by CE# and OE#. If the BYTE# pin is at logic "0", the device is in x8 data configuration: only data I/O pins DQ0-DQ7 are active and controlled by CE# and OE#. The remaining data pins DQ8DQ14 are at Hi-Z, while pin DQ15 is used as the address input A-1 for the Least Significant Bit of the address bus.
Write Operation Status Detection
These devices provide one hardware and two software means to detect the completion of a Write (Program or Erase) cycle in order to optimize the system Write cycle time. The hardware detection uses the Ready/Busy# (RY/ BY#) output pin. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation.
Data# Polling (DQ7)
When the devices are in an internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. During internal Erase operation, any attempt to read DQ7 will produce a `0'. Once the internal Erase operation is completed, DQ7 will produce a `1'. The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block-, or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 10 for Data# Polling (DQ7) timing diagram and Figure 24 for a flowchart.
(c)2006 Silicon Storage Technology, Inc.
S71249-06-000
1/06
3
16 Mbit Dual-Bank Flash Memory SST36VF1601C / SST36VF1602C
Data Sheet
Toggle Bits (DQ6 and DQ2)
During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating "1"s and "0"s, i.e., toggling between 1 and 0. When the internal Program or Erase operation is completed, the DQ6 bit will stop toggling. The device is then ready for the next operation. The toggle bit is valid after the rising edge of the fourth WE# (or CE#) pulse for Program operations. For Sector-, Block-, or Chip-Erase, the toggle bit (DQ6) is valid after the rising edge of sixth WE# (or CE#) pulse. DQ6 will be set to "1" if a Read operation is attempted on an Erase-suspended Sector/Block. If Program operation is initiated in a sector/block not selected in Erase-Suspend mode, DQ6 will toggle. An additional Toggle Bit is available on DQ2, which can be used in conjunction with DQ6 to check whether a particular sector is being actively erased or erase-suspended. Table 1 shows detailed status bit information. The Toggle Bit (DQ2) is valid after the rising edge of the last WE# (or CE#) pulse of a Write operation. See Figure 11 for Toggle Bit timing diagram and Figure 24 for a flowchart. TABLE 1: WRITE OPERATION STATUS
Status Normal Standard Operation Program Standard Erase EraseSuspend Mode Read From Erase Suspended Sector/Block Read From Non-Erase Suspended Sector/Block Program DQ7 DQ7# 0 1 DQ6 Toggle Toggle 1 DQ2 No Toggle Toggle Toggle RY/BY# 0 0 1
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a Write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V. Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down.
Hardware Block Protection
The devices provide hardware block protection which protects the outermost 8 KWord in the larger bank. The block is protected when WP# is held low. See Figures 1, 2, 3, and 4 for Block-Protection location. A user can disable block protection by driving WP# high. This allows data to be erased or programmed into the protected sectors. WP# must be held high prior to issuing the Write command and remain stable until after the entire Write operation has completed.
Hardware Reset (RST#)
The RST# pin provides a hardware method of resetting the devices to read array data. When the RST# pin is held low for at least TRP, any in-progress operation will terminate and return to Read mode (see Figure 20). When no internal Program/Erase operation is in progress, a minimum period of TRHR is required after RST# is driven high before a valid Read can take place (see Figure 19). The Erase operation that has been interrupted needs to be re-initiated after the device resumes normal operation mode to ensure data integrity.
Data
Data
Data
1
DQ7#
Toggle
No Toggle
0
T1.2 1249
Software Data Protection (SDP)
These devices provide the JEDEC standard Software Data Protection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of the three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of the six-byte sequence. The devices are shipped with the Software Data Protection permanently enabled. See Table 5 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to Read mode within TRC. The contents of DQ15-DQ8 can be VIL or VIH, but no other value during any SDP command sequence.
Note: DQ7, DQ6, and DQ2 require a valid address when reading status information.
Data Protection
The devices provide both hardware and software features to protect nonvolatile data from inadvertent writes.
(c)2006 Silicon Storage Technology, Inc.
S71249-06-000
1/06
4
16 Mbit Dual-Bank Flash Memory SST36VF1601C / SST36VF1602C
Data Sheet
Common Flash Memory Interface (CFI)
These devices also contain the CFI information to describe the characteristics of the devices. In order to enter the CFI Query mode, the system must write the three-byte sequence, same as the Software ID Entry command with 98H (CFI Query command) to address 555H in the last byte sequence. See Figure 16 for CFI Entry and Read timing diagram. Once the device enters the CFI Query mode, the system can read CFI data at the addresses given in Tables 6 through 8. The system must write the CFI Exit command to return to Read mode from the CFI Query mode.
Product Identification
The Product Identification mode identifies the devices and manufacturer. For details, see Table 2 for software operation, Figure 15 for the Software ID Entry and Read timing diagram and Figure 25 for the Software ID Entry command sequence flowchart. The addresses A19 and A18 indicate a bank address. When the addressed bank is switched to Product Identification mode, it is possible to read another address from the same bank without issuing a new Software ID Entry command. TABLE 2: PRODUCT IDENTIFICATION
Address Manufacturer's ID Device ID SST36VF1601C SST36VF1602C
Note: BK = Bank Address (A19-A18)
Security ID
The SST36VF160xC devices offer a 256-bit Security ID space. The Secure ID space is divided into two 128-bit segments--one factory programmed segment and one user programmed segment. The first segment is programmed and locked at SST with a unique, 128-bit number. The user segment is left un-programmed for the customer to program as desired. To program the user segment of the Security ID, the user must use the Security ID Program command. End-of-Write status is checked by reading the toggle bits. Data# Polling is not used for Security ID End-ofWrite detection. Once programming is complete, the Sec ID should be locked using the User Sec ID Program LockOut. This disables any future corruption of this space. Note that regardless of whether or not the Sec ID is locked, neither Sec ID segment can be erased. The Secure ID space can be queried by executing a three-byte command sequence with Query Sec ID command (88H) at address 555H in the last byte sequence. See Figure 18 for timing diagram. To exit this mode, the Exit Sec ID command should be executed. Refer to Table 5 for more details.
Data 00BFH 734BH 734AH
T2.0 1249
BK0000H BK0001H BK0001H
Product Identification Mode Exit/CFI Mode Exit
In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to the Read mode. This command may also be used to reset the device to the Read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. Please note that the Software ID Exit/CFI Exit command is ignored during an internal Program or Erase operation. See Table 5 for the software command code, Figure 17 for timing waveform and Figure 26 for a flowchart.
FUNCTIONAL BLOCK DIAGRAM
Memory Address Address Buffers (8 KWord Sector Protection) SuperFlash Memory 12 Mbit Bank BYTE# RST# CE# WP# WE# OE# RY/BY#
1249 B1.0
SuperFlash Memory 4 Mbit Bank Control Logic I/O Buffers
DQ15/A-1 - DQ0
(c)2006 Silicon Storage Technology, Inc.
S71249-06-000
1/06
5
16 Mbit Dual-Bank Flash Memory SST36VF1601C / SST36VF1602C
Data Sheet
Bottom Sector Protection; 32 KWord Blocks; 2 KWord Sectors
FFFFFH F8000H F7FFFH F0000H EFFFFH E8000H E7FFFH E0000H DFFFFH D8000H D7FFFH D0000H CFFFFH C8000H C7FFFH C0000H BFFFFH B8000H B7FFFH B0000H AFFFFH A8000H A7FFFH A0000H 9FFFFH 98000H 97FFFH 90000H 8FFFFH 88000H 87FFFH 80000H 7FFFFH 78000H 77FFFH 70000H 6FFFFH 68000H 67FFFH 60000H 5FFFFH 58000H 57FFFH 50000H 4FFFFH 48000H 47FFFH 40000H 3FFFFH 38000H 37FFFH 30000H 2FFFFH 28000H 27FFFH 20000H 1FFFFH 18000H 17FFFH 10000H 0FFFFH 08000H 07FFFH 02000H 01FFFH 00000H Block 31 Block 30 Block 29
Bank 2 Bank 1
Block 28 Block 27 Block 26 Block 25 Block 24 Block 23 Block 22 Block 21 Block 20 Block 19 Block 18 Block 17 Block 16 Block 15 Block 14 Block 13 Block 12 Block 11 Block 10 Block 9 Block 8 Block 7 Block 6 Block 5 Block 4 Block 3 Block 2 Block 1
8 KWord Sector Protection (4-2 KWord Sectors)
Block 0
1249 F01.0
Note: The address input range in x16 mode (BYTE#=VIH) is A19-A0
FIGURE 1: SST36VF1601C, 1M X16 DUAL-BANK FLASH MEMORY ORGANIZATION
(c)2006 Silicon Storage Technology, Inc. S71249-06-000 1/06
6
16 Mbit Dual-Bank Flash Memory SST36VF1601C / SST36VF1602C
Data Sheet
Bottom Sector Protection; 64 KByte Blocks; 4 KByte Sectors
1FFFFFH 1F0000H 1EFFFFH 1E0000H 1DFFFFH 1D0000H 1CFFFFH 1C0000H 1BFFFFH 1B0000H 1AFFFFH 1A0000H 19FFFFH 190000H 18FFFFH 180000H 17FFFFH 170000H 16FFFFH 160000H 15FFFFH 150000H 14FFFFH 140000H 13FFFFH 130000H 12FFFFH 120000H 11FFFFH 110000H 10FFFFH 100000H 0FFFFFH 0F0000H 0EFFFFH 0E0000H 0DFFFFH 0D0000H 0CFFFFH 0C0000H 0BFFFFH 0B0000H 0AFFFFH 0A0000H 09FFFFH 090000H 08FFFFH 080000H 07FFFFH 070000H 06FFFFH 060000H 05FFFFH 050000H 04FFFFH 040000H 03FFFFH 030000H 02FFFFH 020000H 01FFFFH 010000H 00FFFFH 004000H 003FFFH 000000H Block 31 Block 30 Block 29
Bank 2 Bank 1
Block 28 Block 27 Block 26 Block 25 Block 24 Block 23 Block 22 Block 21 Block 20 Block 19 Block 18 Block 17 Block 16 Block 15 Block 14 Block 13 Block 12 Block 11 Block 10 Block 9 Block 8 Block 7 Block 6 Block 5 Block 4 Block 3 Block 2 Block 1
16 KByte Sector Protection (4-4 KByte Sectors)
Block 0
1249 F01b.0
Note: The address input range in x8 mode (BYTE#=VIL) is A19-A-1
FIGURE 2: SST36VF1601C, 2M X8 DUAL-BANK FLASH MEMORY ORGANIZATION
(c)2006 Silicon Storage Technology, Inc. S71249-06-000 1/06
7
16 Mbit Dual-Bank Flash Memory SST36VF1601C / SST36VF1602C
Data Sheet
Top Block Protection; 32 KWord Blocks; 2 KWord Sectors
8 KWord Block Protection (4 - 2 KWord Sectors)
FFFFFH FE000H FDFFFH F8000H F7FFFH F0000H EFFFFH E8000H E7FFFH E0000H DFFFFH D8000H D7FFFH D0000H CFFFFH C8000H C7FFFH C0000H BFFFFH B8000H B7FFFH B0000H AFFFFH A8000H A7FFFH A0000H 9FFFFH 98000H 97FFFH 90000H 8FFFFH 88000H 87FFFH 80000H 7FFFFH 78000H 77FFFH 70000H 6FFFFH 68000H 67FFFH 60000H 5FFFFH 58000H 57FFFH 50000H 4FFFFH 48000H 47FFFH 40000H 3FFFFH 38000H 37FFFH 30000H 2FFFFH 28000H 27FFFH 20000H 1FFFFH 18000H 17FFFH 10000H 0FFFFH 08000H 07FFFH 00000H Block 31
Block 30 Block 29 Block 28 Block 27 Block 26 Block 25 Block 24 Block 23 Block 22
Bank 2 Bank 1
1249 F02.0
Block 21 Block 20 Block 19 Block 18 Block 17 Block 16 Block 15 Block 14 Block 13 Block 12 Block 11 Block 10 Block 9 Block 8 Block 7 Block 6 Block 5 Block 4 Block 3 Block 2 Block 1 Block 0
Note: The address input range in x16 mode (BYTE#=VIH) is A19-A0
FIGURE 3: SST36VF1602C, 1M X16 DUAL-BANK FLASH MEMORY ORGANIZATION
(c)2006 Silicon Storage Technology, Inc. S71249-06-000 1/06
8
16 Mbit Dual-Bank Flash Memory SST36VF1601C / SST36VF1602C
Data Sheet
Top Block Protection; 64 KByte Blocks; 4 KByte Sectors
16 KByte Block Protection (4 - 4 KByte Sectors)
1FFFFFH 1FC000H 1FBFFFH 1F0000H 1EFFFFH 1E0000H 1DFFFFH 1D0000H 1CFFFFH 1C0000H 1BFFFFH 1B0000H 1AFFFFH 1A0000H 19FFFFH 190000H 18FFFFH 180000H 17FFFFH 170000H 16FFFFH 160000H 15FFFFH 150000H 14FFFFH 140000H 13FFFFH 130000H 12FFFFH 120000H 11FFFFH 110000H 10FFFFH 100000H 0FFFFFH 0F0000H 0EFFFFH 0E0000H 0DFFFFH 0D0000H 0CFFFFH 0C0000H 0BFFFFH 0B0000H 0AFFFFH 0A0000H 09FFFFH 090000H 08FFFFH 080000H 07FFFFH 070000H 06FFFFH 060000H 05FFFFH 050000H 04FFFFH 040000H 03FFFFH 030000H 02FFFFH 020000H 01FFFFH 010000H 00FFFFH 000000H Block 31
Block 30 Block 29 Block 28 Block 27 Block 26 Block 25 Block 24 Block 23 Block 22
Bank 2 Bank 1
1249 F02b.0
Block 21 Block 20 Block 19 Block 18 Block 17 Block 16 Block 15 Block 14 Block 13 Block 12 Block 11 Block 10 Block 9 Block 8 Block 7 Block 6 Block 5 Block 4 Block 3 Block 2 Block 1 Block 0
Note: The address input range in x8 mode (BYTE#=VIL) is A19-A-1
FIGURE 4: SST36VF1602C, 2M X8 DUAL-BANK FLASH MEMORY ORGANIZATION
(c)2006 Silicon Storage Technology, Inc. S71249-06-000 1/06
9
16 Mbit Dual-Bank Flash Memory SST36VF1601C / SST36VF1602C
Data Sheet
TOP VIEW (balls facing down)
6 5 4
A13 A12 A14 A15 A16 BYTE# A9 A8
NOTE*
VSS
A10 A11 DQ7 DQ14 DQ13 DQ6 A19 DQ5 DQ12 VDD DQ4 NC DQ2 DQ10 DQ11 DQ3 A5 A1 DQ0 DQ8 DQ9 DQ1 A0 CE# OE# VSS
1249 48-tfbga P1.0
WE# RST# NC
3
RY/BY# WP# A18
2 1
A7 A3 A17 A4 A6 A2
A
B
C
D
E
F
G
H
Note* = DQ15/A-1
FIGURE 5: PIN ASSIGNMENTS FOR 48-BALL TFBGA (6MM X 8MM)
A15 A14 A13 A12 A11 A10 A9 A8 A19 NC WE# RST# NC WP# RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Standard Pinout Top View Die Up
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VDD DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0
1249 48-tsop P2.0
FIGURE 6: PIN ASSIGNMENTS FOR 48-LEAD TSOP (12MM X 20MM)
(c)2006 Silicon Storage Technology, Inc.
S71249-06-000
1/06
10
16 Mbit Dual-Bank Flash Memory SST36VF1601C / SST36VF1602C
Data Sheet TABLE 3: PIN DESCRIPTION
Symbol A19-A0 Name Address Inputs Functions To provide memory addresses. During Sector-Erase and Hardware Sector Protection, A19-A11 address lines will select the sector. During Block-Erase A19-A15 address lines will select the block. To output data during Read cycles and receive input data during Write cycles Data is internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is high. DQ15 is used as data I/O pin when in x16 mode (BYTE# = "1") A-1 is used as the LSB address pin when in x8 mode (BYTE# = "0") To activate the device when CE# is low. To gate the data output buffers To control the Write operations To reset and return the device to Read mode To output the status of a Program or Erase operation RY/BY# is a open drain output, so a 10K - 100K pull-up resistor is required to allow RY/BY# to transition high indicating the device is ready to read. To protect and unprotect top or bottom 8 KWord (4 outermost sectors) from Erase or Program operation. To provide 2.7-3.6V power supply voltage Unconnected pins
T3.2 1249
DQ14-DQ0 Data Input/Output
DQ15/A-1 CE# OE# WE# RST# RY/BY#
Data Input/Output and LBS Address Chip Enable Output Enable Write Enable Hardware Reset Ready/Busy#
WP# BYTE# VDD VSS NC
Write Protect
Word/Byte Configuration To select 8-bit or 16-bit mode. Power Supply Ground No Connection
TABLE 4: OPERATION MODES SELECTION
DQ15-DQ8 Mode1 Read Program Erase CE# OE# WE# VIL VIL VIL VIL VIH VIH VIH VIL VIL DQ7-DQ0 DOUT DIN X2 BYTE# = VIH DOUT DIN X BYTE# = VIL DQ14-DQ8 = High Z DQ15 = A-1 High Z Address AIN AIN Sector or Block address, 555H for Chip-Erase X X X See Table 5
Standby Write Inhibit Product Identification Software Mode
VIH X X VIL
X VIL X VIL
X X VIH VIH
High Z High Z / DOUT High Z / DOUT Manufacturer's ID (BFH) Device ID3
High Z High Z / DOUT High Z / DOUT Manufacturer's ID (00H) Device ID3
High Z High Z High Z High Z High Z
T4.2 1249
1. RST# = VIH for all described operation modes 2. X can be VIL or VIH, but no other value. 3. Device ID = SST36VF1601C = 734BH, SST36VF1602C = 734AH
(c)2006 Silicon Storage Technology, Inc.
S71249-06-000
1/06
11
16 Mbit Dual-Bank Flash Memory SST36VF1601C / SST36VF1602C
Data Sheet TABLE 5: SOFTWARE COMMAND SEQUENCE
Command Sequence Program Sector-Erase Block-Erase Chip-Erase Erase-Suspend Erase-Resume Query Sec ID5 User Security ID Program User Security ID Program Lock-out7 Software ID Entry8 CFI Query Entry Software ID Exit/ CFI Exit/ Sec ID Exit10,11 Software ID Exit/ CFI Exit/ Sec ID Exit10,11 1st Bus Write Cycle Addr1
555H 555H 555H 555H XXXXH XXXXH 555H 555H 555H 555H 555H 555H
2nd Bus Write Cycle Addr1
2AAH 2AAH 2AAH 2AAH
3rd Bus Write Cycle Addr1
555H 555H 555H 555H
4th Bus Write Cycle Addr1
WA3 555H 555H 555H
5th Bus Write Cycle Addr1
2AAH 2AAH 2AAH
6th Bus Write Cycle Addr1
SAX4 BAX
4
Data2
AAH AAH AAH AAH B0H 30H AAH AAH AAH AAH AAH AAH
Data2
55H 55H 55H 55H
Data2
A0H 80H 80H 80H
Data2
Data AAH AAH AAH
Data2
55H 55H 55H
Data2
30H 50H 10H
555H
2AAH 2AAH 2AAH 2AAH 2AAH 2AAH
55H 55H 55H 55H 55H 55H
555H 555H 555H BKX9 555H BKX9 555H 555H
88H A5H 85H 90H 98H F0H SIWA6 XXH Data 0000H
XXH
F0H
T5.6 1249
1. Address format A11-A0 (Hex), Addresses A19-A12 can be VIL or VIH, but no other value, for the command sequence when in x16 mode. When in x8 mode, Addresses A19-A12, Address A-1 and DQ14-DQ8 can be VIL or VIH, but no other value, for the command sequence. 2. DQ15-DQ8 can be VIL or VIH, but no other value, for the command sequence 3. WA = Program word/byte address 4. SAX for Sector-Erase; uses A19-A11 address lines BAX for Block-Erase; uses A19-A15 address lines 5. For SST36VF1601C, SST ID is read with A3 = 0 (Address range = 00000H to 00007H), User ID is read with A3 = 1 (Address range = 00010H to 00017H). Lock Status is read with A7-A0 = 000FFH. Unlocked: DQ3 = 1 / Locked: DQ3 = 0. For SST36VF1602C, SST ID is read with A3 = 0 (Address range = C0000H to C0007H), User ID is read with A3 = 1 (Address range = C0010H to C0017H). Lock Status is read with A7-A0 = C00FFH. Unlocked: DQ3 = 1 / Locked: DQ3 = 0. 6. SIWA = User Security ID Program word/byte address For SST36VF1601C, valid Word-Addresses for User Sec ID are from 00010H-00017H. For SST36VF1602C, valid Word-Addresses for User Sec ID are from C0010H-C0017H. All 4 cycles of User Security ID Program and Program Lock-out must be completed before going back to Read-Array mode. 7. The User Security ID Program Lock-out command must be executed in x16 mode (BYTE#=VIH). 8. The device does not remain in Software Product Identification mode if powered down. 9. A19 and A18 = BKX (Bank Address): address of the bank that is switched to Software ID/CFI Mode With A17-A1 = 0;SST Manufacturer's ID = 00BFH, is read with A0 = 0 SST36VF1601C Device ID = 734BH, is read with A0 = 1 SST36VF1602C Device ID = 734AH, is read with A0 = 1 10. Both Software ID Exit operations are equivalent 11. If users never lock after programming, User Sec ID can be programmed over the previously unprogrammed bits (data=1) using the User Sec ID mode again (the programmed "0" bits cannot be reversed to "1"). For SST36VF1601C, valid Word-Addresses for User Sec ID are from 00010H-00017H. For SST36VF1602C, valid Word-Addresses for User Sec ID are from C0010H-C0017H.
(c)2006 Silicon Storage Technology, Inc.
S71249-06-000
1/06
12
16 Mbit Dual-Bank Flash Memory SST36VF1601C / SST36VF1602C
Data Sheet TABLE 6: CFI QUERY IDENTIFICATION STRING1
Address x16 Mode 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH Address x8 Mode 20H 22H 24H 26H 28H 2AH 2CH 2EH 30H 32H 34H Data2 0051H 0052H 0059H 0001H 0007H 0000H 0000H 0000H 0000H 0000H 0000H Description Query Unique ASCII string "QRY"
Primary OEM command set Address for Primary Extended Table Alternate OEM command set (00H = none exists) Address for Alternate OEM extended Table (00H = none exits)
T6.2 1249
1. Refer to CFI publication 100 for more details. 2. In x8 mode, only the lower byte of data is output.
TABLE 7: SYSTEM INTERFACE INFORMATION
Address x16 Mode 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H Address x8 Mode 36H 38H 3AH 3CH 3EH 40H 42H 44H 46H 48H 4AH 4CH Data1 0027H 0036H 0000H 0000H 0004H 0000H 0004H 0006H 0001H 0000H 0001H 0001H Description VDD Min (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts VDD Max (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts VPP min (00H = no VPP pin) VPP max (00H = no VPP pin) Typical time out for Program 2N s (24 = 16 s) Typical time out for min size buffer program 2N s (00H = not supported) Typical time out for individual Sector/Block-Erase 2N ms (24 = 16 ms) Typical time out for Chip-Erase 2N ms (26 = 64 ms) Maximum time out for Program 2N times typical (21 x 24 = 32 s) Maximum time out for buffer program 2N times typical Maximum time out for individual Sector-/Block-Erase 2N times typical (21 x 24 = 32 ms) Maximum time out for Chip-Erase 2N times typical (21 x 26 = 128 ms)
T7.3 1249
1. In x8 mode, only the lower byte of data is output.
(c)2006 Silicon Storage Technology, Inc.
S71249-06-000
1/06
13
16 Mbit Dual-Bank Flash Memory SST36VF1601C / SST36VF1602C
Data Sheet TABLE 8: DEVICE GEOMETRY INFORMATION
Address x16 Mode 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H Address x8 Mode 4EH 50H 52H 54H 56H 58H 5AH 5CH 5EH 60H 62H 64H 66H 68H Data1 0015H 0002H 0000H 0000H 0000H 0002H 00FFH 0003H 0008H 0000H 001FH 0000H 0000H 0001H Description Device size = 2N Bytes (15H = 21; 221 = 2 MByte) Flash Device Interface description; 0002H = x8/x16 asynchronous interface Maximum number of bytes in multi-byte write = 2N (00H = not supported) Number of Erase Sector/Block sizes supported by device Sector Information (y + 1 = Number of sectors; z x 256B = sector size) y = 1023 + 1 = 1024 sectors (03FFH = 1023) z = 8 x 256 Bytes = 2 KByte/sector (0008H = 8) Block Information (y + 1 = Number of blocks; z x 256B = block size) y = 31 + 1 = 32 blocks (001FH = 31) z = 256 x 256 Bytes = 64 KByte/block (0100H = 256)
T8.3 1249
1. In x8 mode, only the lower byte of data is output.
(c)2006 Silicon Storage Technology, Inc.
S71249-06-000
1/06
14
16 Mbit Dual-Bank Flash Memory SST36VF1601C / SST36VF1602C
Data Sheet Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V Package Power Dissipation Capability (TA = 25C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Surface Mount Solder Reflow Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C for 10 seconds Output Short Circuit Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
OPERATING RANGE:
Range Commercial Industrial Ambient Temp 0C to +70C -40C to +85C VDD 2.7-3.6V 2.7-3.6V
AC CONDITIONS OF TEST
Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns Output Load . . . . . . . . . . . . . . . . . . . . CL = 30 pF See Figures 21 and 22
(c)2006 Silicon Storage Technology, Inc.
S71249-06-000
1/06
15
16 Mbit Dual-Bank Flash Memory SST36VF1601C / SST36VF1602C
Data Sheet TABLE 9: DC OPERATING CHARACTERISTICS VDD = 2.7-3.6V
Limits Symbol IDD1 Parameter Active VDD Current Read Program and Erase ISB IALP Standby VDD Current Auto Low Power VDD Current 5 MHz 1 MHz 15 10 40 20 20 mA mA mA A A CE#=OE#=VIL, WE#=VIH, All I/Os open CE#=WE#=VIL, OE#=VIH CE#, RST#=VDD0.3V CE#=0.1V, VDD=VDD Max WE#=VDD-0.1V Address inputs=0.1V or VDD-0.1V RST#=GND VIN =GND to VDD, VDD=VDD Max WP#=GND to VDD, VDD=VDD Max RST#=GND to VDD, VDD=VDD Max VOUT =GND to VDD, VDD=VDD Max VDD=VDD Min VDD=VDD Max VDD=VDD Max VDD=VDD Max IOL=100 A, VDD=VDD Min IOH=-100 A, VDD=VDD Min
T9.3 1249
Freq
Min
Max
Units
Test Conditions
IRT ILI ILIW ILO VIL VILC VIH VIHC VOL VOH
Reset VDD Current Input Leakage Current Input Leakage Current on WP# pin and RST# pin Output Leakage Current Input Low Voltage Input Low Voltage (CMOS) Input High Voltage Input High Voltage (CMOS) Output Low Voltage Output High Voltage VDD-0.2 0.7 VDD VDD-0.3
20 1 10 1 0.8 0.3
A A A A V V V V
0.2
V V
1. Address input = VILT/VIHT, VDD=VDD Max (See Figure 21)
TABLE 10: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol TPU-READ
1
Parameter Power-up to Read Operation Power-up to Write Operation
Minimum 100 100
Units s s
T10.0 1249
TPU-WRITE1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 11: CAPACITANCE (TA = 25C, f=1 Mhz, other pins open)
Parameter CI/O1 CIN
1
Description I/O Pin Capacitance Input Capacitance
Test Condition VI/O = 0V VIN = 0V
Maximum 10 pF 10 pF
T11.0 1249
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 12: RELIABILITY CHARACTERISTICS
Symbol NEND TDR1 ILTH1
1
Parameter Endurance Data Retention Latch Up
Minimum Specification 10,000 100 100 + IDD
Units Cycles Years mA
Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard 78
T12.0 1249
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
(c)2006 Silicon Storage Technology, Inc.
S71249-06-000
1/06
16
16 Mbit Dual-Bank Flash Memory SST36VF1601C / SST36VF1602C
Data Sheet
AC CHARACTERISTICS
TABLE 13: READ CYCLE TIMING PARAMETERS VDD = 2.7-3.6V
Symbol TRC TCE TAA TOE TCLZ1 TOLZ1 TCHZ1 TOHZ1 TOH1 TRP1 TRHR
1
Parameter Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time CE# Low to Active Output OE# Low to Active Output CE# High to High-Z Output OE# High to High-Z Output Output Hold from Address Change RST# Pulse Width RST# High before Read RST# Pin Low to Read Mode
Min 70
Max 70 70 35
Units ns ns ns ns ns ns
0 0 20 20 0 500 50 20
ns ns ns ns ns s
T13.0 1249
TRY1,2
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 2. This parameter applies to Sector-Erase, Block-Erase, and Program operations. This parameter does not apply to Chip-Erase operations.
TABLE 14: PROGRAM/ERASE CYCLE TIMING PARAMETERS
Symbol TBP TAS TAH TCS TCH TOES TOEH TCP TWP TWPH1 TCPH1 TDS TDH1 TIDA TSE TBE TSCE TES TBY1,2 TBR1
1
Parameter Program Time Address Setup Time Address Hold Time WE# and CE# Setup Time WE# and CE# Hold Time OE# High Setup Time OE# High Hold Time CE# Pulse Width WE# Pulse Width WE# Pulse Width High CE# Pulse Width High Data Setup Time Data Hold Time Software ID Access and Exit Time Sector-Erase Block-Erase Chip-Erase Erase-Suspend Latency RY/BY# Delay Time Bus Recovery Time
Min 0 40 0 0 0 10 40 40 30 30 30 0
Max 10
Units s ns ns ns ns ns ns ns ns ns ns ns ns
150 25 25 50 20 90 0
ns ms ms ms s ns s
T14.1 1249
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 2. This parameter applies to Sector-Erase, Block-Erase, and Program operations. This parameter does not apply to Chip-Erase operations.
(c)2006 Silicon Storage Technology, Inc.
S71249-06-000
1/06
17
16 Mbit Dual-Bank Flash Memory SST36VF1601C / SST36VF1602C
Data Sheet
TRC ADDRESSES
TAA
TCE CE# TOE OE# VIH WE# TCLZ TOH DATA VALID TCHZ HIGH-Z DATA VALID
1249 F04.0
TOLZ
TOHZ
DQ15-0
HIGH-Z
FIGURE 7: READ CYCLE TIMING DIAGRAM
TBP ADDRESSES 555 TAH TWP WE# TAS OE# TCH CE# TCS RY/BY# TDS TDH DQ15-0 XXAA XX55 XXA0 DATA WORD (ADDR/DATA) Note: X can be VIL or VIH, but no other value. VALID
1249 F05.1
2AA
555
ADDR
TWPH
TBY
TBR
FIGURE 8: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
(c)2006 Silicon Storage Technology, Inc.
S71249-06-000
1/06
18
16 Mbit Dual-Bank Flash Memory SST36VF1601C / SST36VF1602C
Data Sheet
TBP ADDRESSES 555 TAH TCP CE# TAS OE# TCH WE# TCS RY/BY# TDS TDH DQ15-0 XXAA XX55 XXA0 DATA WORD (ADDR/DATA) Note: X can be VIL or VIH, but no other value. VALID
1249 F06.1
2AA
555
ADDR
TCPH
TBY
TBR
FIGURE 9: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
ADDRESS A19-0 TCE CE# TOEH OE# TOE WE# TBY RY/BY# TOES
DQ7
DATA
DATA#
DATA#
DATA
1249 F07.1
FIGURE 10: DATA# POLLING TIMING DIAGRAM
(c)2006 Silicon Storage Technology, Inc. S71249-06-000 1/06
19
16 Mbit Dual-Bank Flash Memory SST36VF1601C / SST36VF1602C
Data Sheet
ADDRESSES TCE CE# TOEH OE# TOE
WE# TBR DQ6 TWO READ CYCLES WITH SAME OUTPUTS VALID DATA
1249 F08.0
FIGURE 11: TOGGLE BIT TIMING DIAGRAM
SIX-BYTE CODE FOR CHIP-ERASE ADDRESSES 555 2AA 555 555 2AA 555
TSCE
CE#
OE# TWP WE# TBY RY/BY# TBR
DQ15-0
XXAA
XX55
XX80
XXAA
XX55
XX10
VALID
1249 F09.1
Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are interchageable as long as minimum timings are met. (See Table 14) X can be VIL or VIH, but no other value.
FIGURE 12: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM
(c)2006 Silicon Storage Technology, Inc. S71249-06-000 1/06
20
16 Mbit Dual-Bank Flash Memory SST36VF1601C / SST36VF1602C
Data Sheet
SIX-BYTE CODE FOR BLOCK-ERASE ADDRESSES 555 2AA 555 555 2AA BAX
TBE
CE#
OE# TWP WE# TBY RY/BY# TBR
DQ15-0
XXAA
XX55
XX80
XXAA
XX55
XX50
VALID
1249 F10.1
Note: This device also supports CE# controlled Block-Erase operation. The WE# and CE# signals are interchageable as long as minimum timings are met. (See Table 14) BAX = Block Address X can be VIL or VIH, but no other value.
FIGURE 13: WE# CONTROLLED BLOCK-ERASE TIMING DIAGRAM
SIX-BYTE CODE FOR SECTOR-ERASE ADDRESSES 555 2AA 555 555 2AA SAX
TSE
CE#
OE# TWP WE# TBR TBY RY/BY#
DQ15-0
XXAA
XX55
XX80
XXAA
XX55
XX30
VALID
1249 F11.1
Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are interchageable as long as minimum timings are met. (See Table 14) SAX = Sector Address X can be VIL or VIH, but no other value.
FIGURE 14: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM
(c)2006 Silicon Storage Technology, Inc. S71249-06-000 1/06
21
16 Mbit Dual-Bank Flash Memory SST36VF1601C / SST36VF1602C
Data Sheet
THREE-BYTE SEQUENCE FOR SOFTWARE ID ENTRY ADDRESSES 555 2AA 555 0000 0001
CE#
OE# TWP WE# TWPH DQ15-0 XXAA XX55 XX90 TAA 00BF
Device ID
1249 F12.1
TIDA
Device ID = 734BH for SST36VF1601C and 734AH for SST36VF1602C Note: X can be VIL or VIH, but no other value.
FIGURE 15: SOFTWARE ID ENTRY AND READ
THREE-BYTE SEQUENCE FOR CFI QUERY ENTRY ADDRESSES 555 2AA 555
CE#
OE# TWP WE# TWPH DQ15-0 XXAA XX55 XX98
1249 F13.1
TIDA
TAA
Note: X can be VIL or VIH, but no other value.
FIGURE 16: CFI ENTRY AND READ
(c)2006 Silicon Storage Technology, Inc. S71249-06-000 1/06
22
16 Mbit Dual-Bank Flash Memory SST36VF1601C / SST36VF1602C
Data Sheet
THREE-BYTE SEQUENCE FOR SOFTWARE ID EXIT AND RESET
ADDRESSES
555
2AA
555
DQ15-0
XXAA
XX55
XXF0 TIDA
CE#
OE# TWP WE# TWPH
1249 F14.1
Note: X can be VIL or VIH, but no other value.
FIGURE 17: SOFTWARE ID EXIT/CFI EXIT
THREE-BYTE SEQUENCE FOR CFI QUERY ENTRY ADDRESS A19-0 555 2AA 555
CE#
OE# TWP WE# TWPH DQ15-0 XXAA SW0 XX55 SW1 XX88 SW2
1249 F15.1
TIDA
TAA
Note: WP# must be held in proper logic state (VIL or VIH) 1 s prior to and 1 s after the command sequence X can be VIL or VIH, but no other value.
FIGURE 18: SEC ID ENTRY
(c)2006 Silicon Storage Technology, Inc.
S71249-06-000
1/06
23
16 Mbit Dual-Bank Flash Memory SST36VF1601C / SST36VF1602C
Data Sheet
RY/BY# 0V RST# TRP
CE#/OE# TRHR
1249 F16.0
FIGURE 19: RST# TIMING DIAGRAM (WHEN NO INTERNAL OPERATION IS IN PROGRESS)
TRY RY/BY# RST#
TRP CE# OE#
1249 F17.0
TBR
FIGURE 20: RST# TIMING DIAGRAM (DURING SECTOR- OR BLOCK-ERASE OPERATION)
(c)2006 Silicon Storage Technology, Inc.
S71249-06-000
1/06
24
16 Mbit Dual-Bank Flash Memory SST36VF1601C / SST36VF1602C
Data Sheet
VIHT
INPUT
VIT
REFERENCE POINTS
VOT
OUTPUT
VILT
1249 F18.0
AC test inputs are driven at VIHT (0.9 VDD) for a logic "1" and VILT (0.1 VDD) for a logic "0". Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% 90%) are <5 ns.
Note: VIT - VINPUT Test VOT - VOUTPUT Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test
FIGURE 21: AC INPUT/OUTPUT REFERENCE WAVEFORMS
TO TESTER
TO DUT CL
1249 F19.0
FIGURE 22: A TEST LOAD EXAMPLE
(c)2006 Silicon Storage Technology, Inc.
S71249-06-000
1/06
25
16 Mbit Dual-Bank Flash Memory SST36VF1601C / SST36VF1602C
Data Sheet
Start
Load data: XXAAH Address: 555H
Load data: XX55H Address: 2AAH
Load data: XXA0H Address: 555H
Load Address/Data
Wait for end of Program (TBP, Data# Polling bit, or Toggle bit operation) Program Completed
1249 F20.2
Note: X can be VIL or VIH, but no other value.
FIGURE 23: PROGRAM ALGORITHM
(c)2006 Silicon Storage Technology, Inc.
S71249-06-000
1/06
26
16 Mbit Dual-Bank Flash Memory SST36VF1601C / SST36VF1602C
Data Sheet
Internal Timer Program/Erase Initiated
Toggle Bit Program/Erase Initiated
Data# Polling Program/Erase Initiated
Wait TBP, TSCE, TSE or TBE
Read byte/word
Read DQ7
Program/Erase Completed
Read same byte/word
No
Is DQ7 = true data? Yes
No
Does DQ6 match? Yes Program/Erase Completed
Program/Erase Completed
1249 F21.1
FIGURE 24: WAIT OPTIONS
(c)2006 Silicon Storage Technology, Inc.
S71249-06-000
1/06
27
16 Mbit Dual-Bank Flash Memory SST36VF1601C / SST36VF1602C
Data Sheet
Software Product ID Entry Command Sequence Load data: XXAAH Address: 555H
CFI Query Entry Command Sequence
Sec ID Query Entry Command Sequence
Load data: XXAAH Address: 555H
Load data: XXAAH Address: 555H
Load data: XX55H Address: 2AAH
Load data: XX55H Address: 2AAH
Load data: XX55H Address: 2AAH
Load data: XX90H Address: 555H
Load data: XX98H Address: 555H
Load data: XX88H Address: 555H
Wait TIDA
Wait TIDA
Wait TIDA
Read Software ID
Read CFI data
Read Sec ID
X can be VIL or VIH, but no other value
1249 F22.2
FIGURE 25: SOFTWARE PRODUCT ID/CFI/SEC ID ENTRY COMMAND FLOWCHARTS
(c)2006 Silicon Storage Technology, Inc.
S71249-06-000
1/06
28
16 Mbit Dual-Bank Flash Memory SST36VF1601C / SST36VF1602C
Data Sheet
Software ID Exit/CFI Exit/Sec ID Exit Command Sequence
Load data: XXAAH Address: 555H
Load data: XXF0H Address: XXH
Load data: XX55H Address: 2AAH
Wait TIDA
Load data: XXF0H Address: 555H
Return to normal operation
Wait TIDA
Return to normal operation
X can be VIL or VIH, but no other value
1249 F23.1
FIGURE 26: SOFTWARE PRODUCT ID/CFI/SEC ID EXIT COMMAND FLOWCHARTS
(c)2006 Silicon Storage Technology, Inc.
S71249-06-000
1/06
29
16 Mbit Dual-Bank Flash Memory SST36VF1601C / SST36VF1602C
Data Sheet
Chip-Erase Command Sequence Load data: XXAAH Address: 555H
Sector-Erase Command Sequence Load data: XXAAH Address: 555H
Block-Erase Command Sequence Load data: XXAAH Address: 555H
Load data: XX55H Address: 2AAH
Load data: XX55H Address: 2AAH
Load data: XX55H Address: 2AAH
Load data: XX80H Address: 555H
Load data: XX80H Address: 555H
Load data: XX80H Address: 555H
Load data: XXAAH Address: 555H
Load data: XXAAH Address: 555H
Load data: XXAAH Address: 555H
Load data: XX55H Address: 2AAH
Load data: XX55H Address: 2AAH
Load data: XX55H Address: 2AAH
Load data: XX10H Address: 555H
Load data: XX30H Address: SAX
Load data: XX50H Address: BAX
Wait TSCE
Wait TSE
Wait TBE
Chip erased to FFFFH
Sector erased to FFFFH
Block erased to FFFFH
1249 F24.1
Note: X can be VIL or VIH, but no other value.
FIGURE 27: ERASE COMMAND SEQUENCE
(c)2006 Silicon Storage Technology, Inc.
S71249-06-000
1/06
30
16 Mbit Dual-Bank Flash Memory SST36VF1601C / SST36VF1602C
Data Sheet
PRODUCT ORDERING INFORMATION
SST 36 XX VF 1601C - 70 XX XXXXX - XXX 4C XX - B3K - XXX E X Environmental Attribute E1 = non-Pb Package Modifier K = 48 balls or leads Package Type B3 = TFBGA (6mm x 8mm) E =TSOP (type 1, die up, 12mm x 20mm) Temperature Range C = Commercial = 0C to +70C I = Industrial = -40C to +85C Minimum Endurance 4 = 10,000 cycles Read Access Speed 70 = 70 ns Bank Split 1 = 12 Mbit + 4 Mbit 2 = 4 Mbit + 12 Mbit Device Density 160 = 1Mbit x16 or 2Mbit x8 Voltage V = 2.7-3.6V Product Series 36 = Dual-Bank Flash Memory
1. Environmental suffix "E" denotes non-Pb solder. SST non-Pb solder devices are "RoHS Compliant".
Valid combinations for SST36VF1601C SST36VF1601C-70-4C-B3KE SST36VF1601C-70-4I-B3KE SST36VF1601C-70-4C-EKE SST36VF1601C-70-4I-EKE
Valid combinations for SST36VF1602C SST36VF1602C-70-4C-B3KE SST36VF1602C-70-4I-B3KE SST36VF1602C-70-4C-EKE SST36VF1602C-70-4I-EKE
Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations.
(c)2006 Silicon Storage Technology, Inc.
S71249-06-000
1/06
31
16 Mbit Dual-Bank Flash Memory SST36VF1601C / SST36VF1602C
Data Sheet
PACKAGING DIAGRAMS
TOP VIEW
8.00 0.20
BOTTOM VIEW
5.60 0.80 0.45 0.05 (48X)
6 5 4 3 2 1
0.80 ABCDEFGH A1 CORNER HGFEDCBA 4.00 6.00 0.20
6 5 4 3 2 1
SIDE VIEW
1.10 0.10
A1 CORNER
SEATING PLANE 0.35 0.05
0.12
1mm
Note:
1. Complies with JEDEC Publication 95, MO-210, variant 'AB-1', although some dimensions may be more stringent. 2. All linear dimensions are in millimeters. 3. Coplanarity: 0.12 mm 4. Ball opening size is 0.38 mm ( 0.05 mm) 48-tfbga-B3K-6x8-450mic-4
48-BALL THIN-PROFILE, FINE-PITCH BALL GRID ARRAY (TFBGA) 6MM X 8MM SST PACKAGE CODE: B3K
(c)2006 Silicon Storage Technology, Inc.
S71249-06-000
1/06
32
16 Mbit Dual-Bank Flash Memory SST36VF1601C / SST36VF1602C
Data Sheet
1.05 0.95 Pin # 1 Identifier 0.50 BSC
12.20 11.80
0.27 0.17
18.50 18.30
0.15 0.05
DETAIL 1.20 max. 0.70 0.50 20.20 19.80 0- 5 Note: 1. Complies with JEDEC publication 95 MO-142 DD dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (max/min). 3. Coplanarity: 0.1 mm 4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads. 0.70 0.50
1mm 48-tsop-EK-8
48-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 12MM X 20MM SST PACKAGE CODE: EK
(c)2006 Silicon Storage Technology, Inc.
S71249-06-000
1/06
33
16 Mbit Dual-Bank Flash Memory SST36VF1601C / SST36VF1602C
Data Sheet TABLE 15: REVISION HISTORY
Number 00 01 Description Date Oct 2003 Dec 2003
* * * * * * * *
Initial release of data sheet 2004 Data Book Updated B3K package diagram Added MPNs for EK package
02
Clarified Chip-Erase Operation on page 3 Added x8 Mode address maps in Figure 2 and Figure 4 Added footnote for RST# to Table 4 Changes to Table 5 on page 13 - Corrected Word/Byte Program command name - Updated footnotes 1, 5, 6, and 11 for x8 Mode and updated Sec Id Address - Added footnote 7 for the User Security ID Program Lock-out command * Added x8 Mode addresses in CFI Tables 6, 7, and 8 and a footnote * Corrected x8/x16 CFI value in Table 8 on page 15 * Changes to Table 9 on page 17 - Added the ILIW parameter - Corrected the Test Conditions for IRT from RST#=VSS0.3V to RST#=GND - Corrected the Address input from VIL/VIH to VILT/VIHT and added a figure reference * * * * * Removed Chip-Erase from the "Concurrent Read/Write Operation" table footnote Corrected the address lines for Sector-Erase from A19-A10 to A19-A11 in Table 3 and Table 5 Updated software command sequence addresses in Table 5 on page 13, timing diagrams, and flowcharts Changed references to Word-Program and Byte-Program to Program Clarified Surface Mount Temperatures in "Absolute Maximum Stress Ratings" on page 16 Changed title of data sheet from "Concurrent SuperFlash" to "Dual-Bank Flash" Removed references to concurrent bank operations Removed the section, "Concurrent Read/Write Operation" from page 2 Updated sector information in Table 8, "Device Geometry Information" on page 15 Reverted Table 8, "Device Geometry Information" on page 15 to revision 03 (T8.3 1249) Added statement that non-Pb devices are RoHS compliant to Features section Updated Surface Mount Solder Reflow Temperature information Removed leaded part numbers Migrated document to a Data Sheet
Feb 2004
03
Aug 2004
04
* * * * * * * * *
Nov 2004
05 06
Dec 2004 Jan 2006
Silicon Storage Technology, Inc. * 1171 Sonora Court * Sunnyvale, CA 94086 * Telephone 408-735-9110 * Fax 408-735-9036 www.SuperFlash.com or www.sst.com
(c)2006 Silicon Storage Technology, Inc. S71249-06-000 1/06
34

▲Up To Search▲

Price & Availability of SST36VF1601C-70-4C-B3KE

	To Download SST36VF1601C-70-4C-B3KE Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .